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INTEGRATED CIRCUITS
80C562/83C562 Single-chip 8-bit microcontroller
Product specification IC20 Data Handbook 1992 Jan 08
Philips Semiconductors
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
Single-chip 8-bit microcontroller with 8-bit A/D, capture/compare timer, high-speed outputs, PWM
DESCRIPTION
The 80C562/83C562 (hereafter generically referred to as 8XC562) Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 83C562/83C562 has the same instruction set as the 80C51. The 8XC562 contains a non-volatile 256 x 8 read-only program memory, a volatile 256 x 8 read/write data memory (83C562) (the 80C562 is ROMless), a volatile 256 x 8 read/write data memory, six 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, two pulse width modulated outputs, standard 80C51 UART, a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 83C562 can be expanded using standard TTL compatible memories and logic. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. With a 12MHz crystal, 58% of the instructions are executed in 1s and 40% in 2s. Multiply and divide instructions require 4s.
FEATURES
* 80C51 instruction set * 8k x 8 ROM expandable externally to
64k bytes
PIN CONFIGURATION
9 10 PLASTIC LEADED CHIP CARRIER 26 27 43 44 1 61 60
* 256 x 8 RAM, expandable externally to
64k bytes
* Two standard 16-bit timer/counters * An additional 16-bit timer/counter coupled
to four capture registers and three compare registers
* Capable of producing eight synchronized,
timed outputs
* An 8-bit ADC with eight multiplexed analog
inputs
* Two 8-bit resolution, pulse width modulated
outputs
* Five 8-bit I/O ports plus one 8-bit input port
shared with analog inputs
* Full-duplex UART compatible with the
standard 80C51
* On-chip watchdog timer * Three temperature ranges
- 0 to +70C - -40 to +85C - -40 to +125C
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Function P5.0/ADC0 VDD STADC PWM0 PWM1 EW P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST P1.0/CT0I P1.1/CT1I P1.2/CT2I P1.3/CT3I P1.4/T2 P1.5/RT2 P1.6 P1.7 P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD NC NC XTAL2
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Function XTAL1 VSS VSS NC P2.0/A08 P2.1/A09 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 AVref- AVref+ AVSS AVDD P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1
SU00224
1992 Jan 08
2
853-1463 05128
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
ORDERING INFORMATION
PHILIPS PART ORDER NUMBER PART MARKING ROMless ROM PHILIPS NORTH AMERICA PART ORDER NUMBER ROMless ROM S83C562-4A68 Drawing Number SOT188 EPROM S87C552-4A682 S87C552-4K682 PCF80C56212WP PCF83C56212WP/xxx S80C562-2A68 S83C562-2A68 SOT188 S87C552-5A682 Drawing Number SOT188-3 1473A SOT188-3 TEMPERATURE RANGE C AND PACKAGE 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Leaded Chip Carrier w/Window -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Leaded Chip Carrier w/Window -40 to +125, Plastic Leaded Chip Carrier FREQ MHz 16 16 12
PCB80C562- PCB83C562S80C562-4A68 16WP 16WP/xxx
S87C552-5K682 PCA80C562- PCA83C562- S80C562-6A68 S83C562-6A68 SOT188 12WP 12WP/xxx NOTES: 1. 80C562 and 83C562 frequency range is 1.2MHz-12MHz or 1.2MHz-16MHz. 2. 87C552 frequency range is 3.5MHz-16MHz. For full specification, see the 87C552 data sheets. 3. xxx denotes the ROM code number.
1473A
12 12
LOGIC SYMBOL
VSS VDD XTAL1 XTAL2 EA ALE PSEN AVSS AVDD AVref+ AVref- STADC PWM0 PWM1
PORT 0
LOW ORDER ADDRESS AND DATA BUS
CT0I CT1I CT2I CT3I T2 RT2
ADC0-7 PORT 5
PORT 2
PORT 1
HIGH ORDER ADDRESS AND DATA BUS
CMSR0-5 PORT 4 RxD TxD INT0 INT1 T0 T1 WR RD PORT 3
CMT0 CMT1 RST EW
SU00225
1992 Jan 08
3
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
BLOCK DIAGRAM
T0 3 T1 3 INT0 3 INT1 3 VDD VSS PWM0 PWM1 AVSS AVREF ADC0-7 5
-+
AVDD STADC
XTAL1 XTAL2 EA ALE PSEN 3 3 RD 0 AD0-7 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES T2 16-BIT TIMER/ EVENT COUNTERS 16 16 WR T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY 8k x 8 ROM (83C562) DATA MEMORY 256 x 8 RAM DUAL PWM
CPU
ADC
80C51 CORE EXCLUDING ROM/RAM 8-BIT INTERNAL BUS
T2 16-BIT COMPARATORS WITH REGISTERS
COMPARATOR OUTPUT SELECTION
T3 WATCHDOG TIMER
3 P0 P1 P2 P3 TxD
3 RxD P5 P4
1 CT0I-CT3I
1 T2 RT2
1
4 CMSR0-CMSR5 CMT0, CMT1 RST EW
0 1 2
ALTERNATE FUNCTION OF PORT 0 ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2
3 4 5
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
SU00226
1992 Jan 08
4
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
PIN DESCRIPTION
MNEMONIC VDD STADC PWM0 PWM1 EW P0.0-P0.7 PIN NO. 2 3 4 5 6 57-50 TYPE I I O O I I/O NAME AND FUNCTION Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode. Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). Pulse Width Modulation: Output 0. Pulse Width Modulation: Output 1. Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 1: 8-bit I/O port. Alternate functions include: (P1.0-P1.7): Quasi-bidirectional port pins. CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input RT2 (P1.5): T2 timer reset signal. Rising edge triggered. Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC. Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows. Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used. Digital ground. Program Store Enable: Active-low read strobe to external program memory. Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. Analog to Digital Conversion Reference Resistor: Low-end. Analog to Digital Conversion Reference Resistor: High-end. Analog Ground Analog Power Supply
P1.0-P1.7
16-23 16-23 16-19 20 21 39-46 24-31 24 25 26 27 28 29 30 31 7-14 7-12 13, 14 68-62, 1 15 35 34 36, 37 47 48
I/O I/O I/O I I I/O I/O
P2.0-P2.7 P3.0-P3.7
P4.0-P4.7
I/O O O I I/O I O I O O
P5.0-P5.7 RST XTAL1 XTAL2 VSS PSEN ALE
EA
49
I
AVREF- AVREF+ AVSS AVDD
58 59 60 61
I I I I
NOTE: 1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD +0.5V or VSS - 0.5V, respectively.
1992 Jan 08
5
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To ensure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up.
remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register PCON. Table 1 shows the state of the I/O ports during low current operating modes.
IDLE MODE
In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers
Table 1.
MODE Idle Idle Power-down Power-down
External Pin Status During Idle and Power-Down Modes
PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data PORT 4 Data Data Data Data PWM0/ PWM1 High High High High
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Voltage on any other pin to VSS Input, output DC current on any single I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) Storage temperature range RATING -0.5 to +6.5 5.0 1.0 -65 to +150 UNIT V mA W C
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1992 Jan 08
6
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V TEST SYMBOL VDD Supply voltage PCB8XC562 PCF8XC562 PCA8XC562 Supply current operating: PCB8XC562 PCF8XC562 PCA8XC562 Idle mode: PCB8XC562 PCF8XC562 PCA8XC562 Power-down current: PCB8XC562 PCF8XC562 PCA8XC562 Inputs VIL VIL1 VIH VIH1 IIL ITL +IIL1 Outputs VOL VOL1 VOH Output low voltage, ports 1, 2, 3, 4 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 Output high voltage, ports 1, 2, 3, 4 IOL = 1.6mA6 IOL = 3.2mA6 2.4 0.75VDD 0.9VDD VDD + 5V+10% -IOH = 60A -IOH = 25A -IOH = 10A VDD + 5V+10% -IOH = 400A -IOH = 150A -IOH = 40A -IOH = 400A -IOH = 120A 0.45 0.45 V V V V V Input low voltage, except EA Input low voltage to EA Input high voltage, except XTAL1, RST Input high voltage, XTAL1, RST Logical 0 input current, ports 1, 2, 3, 4 Logical 1-to-0 transition current, ports 1, 2, 3, 4 Input leakage current, port 0, EA, STADC, EW VIN = 0.45V See note 5 0.45V < VI < VDD -0.5 -0.5 0.2VDD+0.9 0.7VDD 0.2VDD-0.1 0.2VDD-0.3 VDD+0.5 VDD+0.5 -50 -650 10 V V V V A A A See notes 1 and 2 fOSC = 16MHz fOSC = 12MHz fOSC = 12MHz See notes 1 and 3 fOSC = 16MHz fOSC = 12MHz fOSC = 12MHz See notes 1 and 4; 2V < VPD < VDD max 50 50 100 PARAMETER CONDITIONS MIN 4.0 4.0 4.5 LIMITS MAX 6.0 6.0 5.5 45 34 30 10 8 7 UNIT V V V mA mA mA mA mA mA
IDD
IID
IPD
A A A
VOH1
Output high voltage (port 0 in external bus mode, ALE, PSEN, PWM0, PWM1)7
2.4 0.75VDD 0.9VDD 2.4 0.8VDD 50 150 10
V V V V V k pF
VOH2 RRST CIO
Output high voltage (RST) Internal reset pull-down resistor Pin capacitance
Test freq = 1MHz, Tamb = 25C
1992 Jan 08
7
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST SYMBOL Analog Inputs AVDD Analog supply voltage: PCB8XC562 PCF8XC562 PCA8XC562 Analog supply current: operating: Idle mode: PCB8XC562 PCF8XC562 PCA8XC562 Power-down mode: PCB8XC562 PCF8XC562 PCA8XC562 Analog input voltage Reference voltage: AVREF- AVREF+ Resistance between AVREF+ and AVREF- Analog input capacitance Sampling time Conversion time (including sampling time) Differential non-linearity8, 9, 10 Integral non-linearity8, 11 Offset error8, 12 Gain error8, 13 Channel to channel matching Crosstalk between inputs of port 514 0-100kHz 2V < AVPD < AVDD max 50 50 100 AVSS-0.2 AVSS-0.2 AVDD+0.2 5 25 15 6tCY 24tCY 1 1 1 0.4 1 -60 AVDD+0.2 AVDD = VDD0.2V AVDD = VDD0.2V AVDD = VDD0.2V Port 5 = 0 to AVDD 4.0 4.0 4.5 6.0 6.0 5.5 1.2 50 50 100 V V V mA A A A A A A V V V k pF s s LSB LSB LSB % LSB dB PARAMETER CONDITIONS MIN LIMITS MAX UNIT
AIDD AIID
AIPD
AVIN AVREF
RREF CIA tADS tADC DLe ILe OSe Ge MCTC Ct
NOTES: 1. See Figures 8 through 12 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD - 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VDD - 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 7. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address bits are stabilizing. 8. Conditions: AVREF- = 0V; AVDD = 5.0V, AVREF+ = 5.12V. ADC is monotonic with no missing codes. 9. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 10. The ADC is monotonic; there are no missing codes. 11. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.) 12. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 1.) 13. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.) 14. This should be considered when both analog and digital signals are simultaneously input to port 5.
1992 Jan 08
8
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
Offset error OSe 255
Gain error Ge
254
253
252
251
250 (2)
7 Code Out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal)
0 1 2 3 4 5 6 7 250 251 252 253 254 255 256
AVIN (LSBideal) Offset error OSe (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DLe). (4) Integral non-linearity (ILe). (5) Center of a step of the actual transfer curve.
1 LSB =
AVREF+
- AVREF-
256
SU00227
Figure 1. ADC Conversion Characteristic
1992 Jan 08
9
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
AC ELECTRICAL CHARACTERISTICS1, 2
12MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tAVLL tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL 5 5 5 5 High time3 Low time3 Rise time3 Fall time3 20 20 20 20 20 20 20 20 ns ns ns ns 3, 4 3 4 3 3 3 3 3 3, 4 3, 4 4 4 4 3 3, 4 Address valid to ALE low RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data before WR Data hold after WR RD low to address float RD or WR high to ALE high 43 200 203 23 433 33 0 123 tCLCL-40 0 97 517 585 300 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 0 tCLCL+40 43 400 400 252 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 tCLCL-35 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 59 312 10 43 205 145 0 tCLCL-25 5tCLCL-105 10 127 28 48 234 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 1.2 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested.
1992 Jan 08
10
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
1992 Jan 08
11
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
A0-A7 FROM RI OR DPL
tQVWX tDW
DATA OUT
tWHQX
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
SU00213
Figure 4. External Data Memory Write Cycle
tHIGH VIH1
0.8V
tr VIH1
0.8V
tf VIH1 VIH1
0.8V
0.8V
tLOW tCK
SU00228
Figure 5. External Clock Drive XTAL1
2.4V 2.0V Test Points 0.8V 0.45V NOTE: AC inputs during testing are driven at 2.4V for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at 2.0V for a logic `1' and 0.8V for a logic `0'. 0.8V 2.0V
SU00215
Figure 6. AC Testing Input/Output
Float 2.4V 2.0V 0.8V 2.0V 0.8V 2.4V
0.45V
0.45V
NOTE: The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400A at the voltage test levels.
SU00216
Figure 7. AC Testing Input, Float Waveform
1992 Jan 08
12
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
50 (1) 40
30 IDD mA 20 (2)
10
(3) (4)
0 NOTE: These values are valid only within the frequency specifications of the device under test. 0 4 8 f (MHz) 12 16
(1) (2) (3) (4)
Maximum operating mode; VDD = 6V Maximum operating mode; VDD = 4V Maximum idle mode; VDD = 6V Maximum idle mode; VDD = 4V
SU00229
Figure 8. Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
VDD IDD VDD VDD P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS STADC EW VDD
RST
SU00230
Figure 9. IDD Test Condition, Active Mode All other pins are disconnected
VDD IDD VDD RST STADC P0 EW (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS EA AVSS AVref VDD
SU00231
Figure 10. IDD Test Condition, Idle Mode All other pins are disconnected 1992 Jan 08 13
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
VDD-0.5 0.5V
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00232
Figure 11. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 10ns
VDD IDD VDD RST STADC P0 EW (NC) XTAL2 XTAL1 VSS EA AVSS AVref VDD
SU00233
Figure 12. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2V to 5.5V
1992 Jan 08
14
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
SOT188-3
1992 Jan 08
15
1473A
1992 Jan 08
3.05 (0.120) 2.29 (0.090) 0.38 (0.015) 6 0.51 (0.02) X 45 6
25.27 (0.995) 25.02 (0.985)
Philips Semiconductors
Single-chip 8-bit microcontroller
853-1473A 05854
1.02 (0.040) X 45
24.51 (0.965) 3 23.62 (0.930)
CHAMFER 45
NOTES: 1. All dimensions and tolerances to conform to ANSI Y14.5-1982. 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum on each side. 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only.
25.27 (0.995) 25.02 (0.985) 24.51 (0.965) 23.62 (0.930) 3
2
68-PIN CERQUAD J-BEND (K) PACKAGE
3 X 0.63 (0.025) R MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
0.73 + 0.08 (0.029 + 0.003) 1.27 (0.050) TYP. 0.25 (0.010) R MIN. 1.52 (0.060) REF. 45 TYP. 4 PLACES 0.15 (0.006) MIN.
90
16
1.02 + 0.25 (0.040 + 0.010) BASE PLANE 0.482 (0.019 + 0.002) SEATING PLANE 11.94 (0.470) 11.18 (0.440)
+ 5 -10
25.27 (0.995) 25.02 (0.985)
1.27 (0.050)
64X
0.076 (0.003) MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
SEE DETAIL A
20.32 (0.800) NOMINAL
0.25 (0.010) 0.15 (0.006)
0.508 (0.020) R MIN.
11.94 (0.470) 11.18 (0.440)
DETAIL A TYP. ALL SIDES mm/(inch)
DETAIL B mm/(inch)
SEE DETAIL B
80C562/83C562
Product specification
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
1992 Jan 08
17
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
1992 Jan 08
18
Philips Semiconductors
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
NOTES
1992 Jan 08
19
Philips Semiconductors Microcontroller Products
Product specification
Single-chip 8-bit microcontroller
80C562/83C562
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1992 All rights reserved. Printed in U.S.A.

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